A DRAM-based processing unit (DPU) may be used as an alternative accelerator to other processor and/or graphics accelerators, such as, for example, graphics processing units (GPUs) and application specific integrated circuits (ASICs). A new ecosystem corresponding to DPU may be provided with drivers and libraries designed to achieve improved or optimal mapping and scheduling for DPU.
A DPU may be reconfigurable and programmable. For example, the logic provided by DRAM cells may be configured (or reconfigured) to provide different operations, e.g., adder, multiplier, etc. For example, a DPU may be based on three transistor, one capacitor (3T1C)/one transistor, one capacitor (1T1C) DRAM process and structure with minor modifications. Because DPU typically does not contain specific computing logic (e.g., adders), memory cells may be used for computations.